A parallel optical link is effective in use for expanding the capacity of data connections inside and between the devices contained in a high-performance network apparatus and a computer system. The parallel optical link relates to the connections by a short distance data communication inside and between the devices, and to the communication technology that transmits signals, by driving in parallel optical signal transmission systems composed of optical signal-emitting elements, optical signal-receiving elements, and optical fibers. A use of the parallel optical link will achieve a large throughput data communication connection on a small device scale with a low delay.
To synchronously communicate a large throughput of signals in parallel by using the parallel optical link, it is necessary to compensate the skew between both channels of parallel data and a clock, and to maintain the signal synchronism between the parallel channels. The conventional computer system employs mainly two techniques for the skew compensation between the parallel signals inside the system. One is to compensate a low skew (less than one clock cycle) between the clock and the data by using delay elements and so forth, and the other one is to compensate a high skew (more than one clock cycle) by using logic circuits called the framed synchronization.
The invention belongs to the technique that compensates the low skew between the clock and the data with a high accuracy. The broadband orientation in the data communication accompanies an extraordinary acceleration of the clock speed, and in the year of 2002, the data communication is in the practical use at the clock speed of 10 gigabits per second. The invention is on the premise that it is applied to a large capacity communication using such an extraordinary high-speed clock as 10 gigabits per second.
The following four techniques have been disclosed so far, which compensate the skew between the clock and the data. The first one is to adjust the delay time of the data by means of a multistage gate circuit; the second one is to use a flip-flop circuit; the third one is to use a phase-locked loop circuit; and the fourth one is to shift the phase by means of a differential or integral circuit.
The first technique using the multistage gate circuit is disclosed in the Japanese Patent No.3127882. This technique inputs the data to the multistage gate circuit, and controls a selector to select the output to thereby adjust the skew between the clock and the data.
The second technique using the flip-flop circuit is disclosed in the Japanese Patent Laid-Open No. H10-320074, and in the IEEE Journal of Lightwave Technology, Vol. 12, page 260 to page 270, by Astushi Takai, et al. The Japanese Patent Laid-Open No. H10-320074 employs the circuit system that controls multistage delay lines by a shift register, latches the data signal by two clocks with 180° phase difference, and outputs to select the data signal in the appropriate phase relation. The method that Astushi Takai, et al. reported in the IEEE Journal of Lightwave Technology uses a single stage flip-flop circuit, and latches the data signal by the clock to thereby control the phase between the data and the clock.
The third technique using the phase-locked loop circuit is disclosed in the Japanese Patent Laid-Open No. H10-200401. This technique of adjusting the skew between the clock and the data by using the phase-locked loop circuit or the clock/data recovery circuit having the similar circuit configuration is generally employed in the Ethernet (trademark) and the ATM communication.
The fourth technique using the differential or integral circuit is disclosed in the Japanese Patent Laid-Open No. 2000-101554 and Japanese Patent Laid-Open No. H9-69829. The Japanese Patent Laid-Open No. 2000-101554 possesses the circuit configuration that judges the phase of the clock factor signal extracted from the base clock signal and the received data signal on the basis of the output from the integral circuit. The Japanese Patent Laid-Open No. H9-69829 uses a lowpass filter on the transmitter side, transmits to restrict the frequency factors of the clock signal, and attains the phase shifting. The differential/integral circuit is called the LCR circuit in general, which is capable of shifting the phase analogically by appropriately setting the values of three lumped constant elements of the inductor L, capacitor C, and resistor R.